`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    09:31:38 08/12/2015 
// Design Name: 
// Module Name:    counter 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module counter(
    input clk,
    input clr,
    input en,
	 reg [31:0] cnt_reg,
    output [31:0] cnt
    );

assign cnt = cnt_reg;

always @(posedge clk or posedge clr)
begin
	if (en) begin
		if (clr) cnt_reg <= 0;
		else begin
			cnt_reg <= cnt_reg + 1;
		end
	end
end

endmodule
